package simple_riscv.frontend

import _root_.spinal.lib.bus.amba4.axi.Axi4


object test extends App{
    import spinal.lib._
    import spinal.core._
    import spinal.core.fiber.{Handle, Lock}
    class top extends Component{
        val lock1, lock2 = Lock()
        lock1.retain()
        lock2.retain()
        val io = new Bundle{
            val a = in(UInt(2 bits))
            val b = in(UInt(2 bits))
            val c = out(UInt(2 bits))
        }
        io.c := io.a + io.b
        printf("this is top\n")
        val m = Handle{
            lock1.await()
            val ret = 1
            printf("this is m\n")
            ret
        }
        val n = Handle{
            lock2.await()
            val ret = 1
            printf("this is n\n")
            ret
        }
        // printf("m = %d\n", m.get)
        lock1.release()
        lock2.release()
        Seq(m, n).foreach(_.await())
        printf("this is top, sleep over\n")
    }
    val cfg = SpinalConfig(targetDirectory = "hw/gen") 
    cfg.generateVerilog(new top)
}
